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| Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Analog Marketing: MC33702/D Rev 0, 05/2003 Preliminary Information 3.0 A Switch-Mode Power Supply with Linear Regulator The 33702 provides the means to efficiently supply the Power QUICCTM I, II, and other families of Motorola microprocessors and DSPs. The 33702 incorporates a high-performance switching regulator, providing the direct supply for the microprocessor's core, and a low dropout (LDO) linear regulator control circuit providing the microprocessor I/O and bus voltage. The switching regulator is a high-efficiency synchronous buck regulator with integrated 50 m N-channel power MOSFETs to provide protection features and to allow space-efficient, compact design. The 33702 incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. Features * Operating Voltage: 2.8 V to 6.0 V * High-Accuracy Output Voltages * Fast Transient Response * Switcher Output Current Up to 3.0 A * Undervoltage Lockout * Power Sequencing * Programmable Watchdog Timer * * * * Voltage Margining via Bus Overcurrent Protection Reset with Programmable Power-ON Delay Enable Inputs I2CTM 33702 POWER SUPPLY INTEGRATED CIRCUIT Freescale Semiconductor, Inc... DWB SUFFIX CASE 1324-02 32-LEAD SOICW ORDERING INFORMATION Device PC33702DWB/R2 Temperature Range (TA) -40 to 85C Package 32 SOICW I2C is a trademark of Phillips Corporation. 33702 Simplified Application Diagram 2.8VVtoto 3. 5 V V put 2.8 1 6.0 In MC3 3703 33702 VIN2 VIN2 VIN1 VIN1 O the r Circuits LDRV CS LDO LFB VBD VBD VBST VBST SR RT VLDO = 0.8 t o 5. 0 V (Adjustable) VDDH (I/Os) ADDR SDA SCL GND MPC8XXX MPC85xx PORESET RES ET BO OT SW VBS T EN1 EN2 VOUT = 0.8 to 5.0 V (Adjus table) VDDL (Core) VOUT CLKS YN VOUT CLKS EL PG ND Optional FREQ I NV This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 2003 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. VIN1 VIN1 VIN VIN VDDI VDDI Internal Supply VBST VBST VDDI VDDI VDDI VDDI VBST VBST 8.0V VBST VBST VBD VBD Boost Control Vref Vref Freescale Semiconductor, Inc... EN1 EN2 RESET Reset Control RT POR Timer Reset Power Sequencing Voltage Margining W-dog Timer Watchdog Timer SysCon INV LFB I2C Control SysCon Thermal Limit SoftSt I2C Control ADDR SDA SCL I2C Interface Switcher Oscillator 300kHz Slope Comp. CLKSEL CLKSYN Figure 1. 33702 Simplified Block Diagram 33702 2 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com + + + Vref Power Enable VDDI VDDI VDDI VDDI LDRV CS LDO FREQ Bandgap Voltage Reference VDDI VDDI Linear Regulator Control ILIM I-lim Vref LFB VLDO Pow. Seq. VLDO PWR Seq. Power Down UVLO VOUT VOUT VBST VBST Q4 VBST VBST LCMP BOOT VIN2 VIN2 Current Limit VDDI VDDI (2) Buck HS & LS Driver Q1 SW Q2 (2) PGND Buck Control Logic PWM Comp. + - Error Amp. + - 0.8V To Reset Control VOUT VOUT (2) INV Pow. PWR Seq. Seq. PGND (4) Q3 VOUT VOUT Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... FREQ INV VOUT VIN2 VIN2 SW SW GND GND PGND PGND VBD VBST BOOT SDA SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CLKSYN CLKSEL RESET RT EN2 EN1 ADDR GND GND VDD1 VIN1 LDRV CS LDO LFB LCMP PIN FUNCTION DESCRIPTION Pin 1 Pin Name FREQ Formal Name Oscillator Frequency Definition This selection switcher pin can be adjusted by connecting external resistor RF to the FREQ pin. The default switching frequency (FREQ pin left open or tied to VDDI) is set to 300 kHz. Buck Controller Error Amplifier inverting input. Output voltage of the buck converter. Input pin of the switching regulator power sequence control circuit. Buck regulator power input. Drain of the high-side power MOSFET. Buck regulator switching node. This pin is connected to the inductor. Analog ground of the IC, thermal heatsinking. Buck regulator power ground. Drain of the internal boost regulator power MOSFET. Internal boost regulator output voltage. The internal boost regulator provides a 20 mA output current to supply the drive circuits for the integrated power MOSFETs and the external N-channel power MOSFET of the linear regulator. The voltage at the VBST pin is 8.0 V nominal. Bootstrap capacitor input. I2C bus pin. Serial data. I2C bus pin. Serial clock. Linear regulator compensation pin. Linear regulator feedback pin. Input pin of the linear regulator power sequence control circuit. Current sense pin of the LDO. Overcurrent protection of the linear regulator external power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed between the CS and LDO pins. The LDO current limit can be adjusted by selecting the proper value of the current sensing resistor RS. LDO gate drive of the external pass N-channel MOSFET. The input supply pin for the integrated circuit. The internal circuits of the IC are supplied through this pin. 2 3 4, 5 6, 7 8, 9 24, 25 10, 11 12 13 INV VOUT VIN2 SW Inverting Input Output Voltage Input Voltage 2 Switch Ground Power Ground Boost Drain Boost Voltage GND PGND VBD VBST 14 15 16 17 18 19 20 BOOT SDA Bootstrap Serial Data Serial Clock Linear Compensation Linear Feedback Linear Regulator Current Sense SCL LCMP LFB LDO CS 21 22 LDRV VIN1 Linear Drive Input Voltage 1 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 3 Freescale Semiconductor, Inc. PIN FUNCTION DESCRIPTION (continued) Pin 23 26 Pin Name VDDI ADDR Formal Name Power Supply Address Internal supply voltage. I2C address selection. This pin can be either left open, tied to VDDI, or grounded through a 10 k resistor. Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determine operation mode and type of power sequencing of the IC. Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determine operation mode and type of power sequencing of the IC. This pin allows programming the Power-ON Reset delay by means of an external RC network. The Reset Control circuit monitors both the switching regulator and the LDO feedback voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the LDO) by an external resistor. This pin sets the CLKSYN pin either as an oscillator output or synchronization input pin. The CLKSEL pin is also used for the I2C address selection. 32 CLKSYN Clock Synchronization Oscillator output/synchronization input pin. Definition 27 28 29 30 EN1 EN2 RT RESET Enable 1 Enable 2 Reset Timer Reset Overbar Freescale Semiconductor, Inc... 31 CLKSEL Clock Selection 33702 4 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Supply Voltage Switching Node Buck Regulator Bootstrap Input (BOOT - SW) Boost Regulator Output Boost Regulator Drain RESET Drain Voltage Symbol VIN1, VIN2 SW BOOT VBST VBD RESET - - - - - Value -0.3 to 7.0 -1.0 to 7.0 -0.3 to 8.5 -0.3 to 8.5 -0.3 to 9.5 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 8.5 -0.3 to 3.6 Unit V V V V V V V V V V V V Enable Pins (EN1, EN2) Freescale Semiconductor, Inc... Logic Pins (SDA, SCL, CLKSYN) Analog Pins (INV, VOUT, RESET) Analog Pins (LDRV, LFB, LDO, LCMP, CS) Analog Pins (CLKSEL, ADDR, RT, FREQ, VDDI) ESD Voltage Human Body Model (Note 1) Machine Model (Note 2) Storage Temperature Power Dissipation (TA = 85C) (Note 3) Lead Soldering Temperature (Note 4) Maximum Junction Temperature Thermal Resistance, Junction to Ambient (Note 5) Thermal Resistance, Junction to Base (Note 6) VESD1 VESD2 TSTG PD TSOLDER TJMAX RJA RJB 2000 200 -65 to 150 TBD 260 125 68 18 C W C C C/W C/W OPERATING CONDITIONS Supply Voltage (VIN1, VIN2) Operational Package Temperature (Ambient Temperature) VIN1, VIN2 TA 2.8 to 6.0 -40 to 85 V C Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 ). 2. 3. 4. 5. 6. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 ). Maximum power dissipation at indicated junction temperature. Lead soldering temperature limit is for 10 seconds maximum duration. Contact Motorola Sales Office for device immersion soldering time/ temperature limits. Thermal resistance measured in accordance with EIA/JESD51-2. Theoretical thermal resistance from the die junction to the exposed pins. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 5 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40C TJ 125C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit GENERAL Operating Voltage Range (VIN1, VIN2) Start-Up Voltage Threshold (Boost Switching) VBST Undervoltage Lockout Input DC Supply Current (Normal Operation Mode, Enabled) VIN1 Pin Input Supply Current (EN1 = EN2 = 0) VIN VST VBST_UVLO IIN IIN1 IIN2 VDDI IDDI 2.8 - - - - - 3.0 - - 1.6 6.0 60 9.0 TBD - TBD 6.0 1.8 - - - - 3.3 - V V V mA mA A V A Freescale Semiconductor, Inc... VIN2 Pin Input Leakage Current (EN1 = EN2 = 0) VDDI Internal Supply Voltage VDDI Maximum Output Current BUCK CONVERTER Buck Converter Output Voltage Range IVOUT = 30 mA to 3.0 A, VIN1 = VIN2 = 2.8 V to 6.0 V Buck Converter Feedback Voltage IVOUT = 30 mA to 3.0 A, VIN1 = VIN2 = 2.8 V to 6.0 V. No RB Resistor. Includes Load Regulation Error Buck Converter Voltage Margining Step Buck Converter Line Regulation VIN1 = VIN2 = 2.8 V to 6.0 V, IVOUT = 3.0 A Buck Converter Load Regulation IVOUT = 30 mA to 3.0 A VOUT Input Leakage Current VOUT = 5.0 V High-Side Power MOSFET Q1 RDS(ON) ID = 1.0 A, TA = 25C, VBST = 8.0 V Low-Side Power MOSFET Q2 RDS(ON) ID = 1.0 A, TA = 25C, VBST = 8.0 V Buck Converter Peak Current Limit (High Level) Buck Converter Valley Current Limit (Low Level) VOUT Pull-Down MOSFET Q3 Current Limit TA = 25C, VBST = 8.0 V VOUT Pull-Down MOSFET Q3 RDS(ON) ID = 1.0 A, TA = 25C, VBST = 8.0 V Thermal Shutdown (Switcher, VOUT FET) Thermal Shutdown Hysteresis TSD TSDHys RDS(ON) - 150 - - 170 15 1.0 190 - C C IH_LIM IL_LIM IQ3_LIM - 2.0 - RDS(ON) - 3.4 1.7 - 4.5 2.25 50 6.0 3.0 A A A RDS(ON) - - 50 m IVOUTLK - TBD - m REGLDVO -1.0 - 1.0 A VMVO REGLNVO -1.0 - 1.0 % VINV 0.784 - 0.8 1.0 0.816 - % % VOUT 0.8 - 5.0 V V 33702 6 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40C TJ 125C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit ERROR AMPLIFIER (BUCK CONVERTER) Input Impedance (Note 7) Output Impedance (Note 7) DC Open Loop Gain (Note 7) Gain Bandwidth Product (Note 7) Slew Rate (Note 7) RIN ROUT AVOL GBW SR VEA_OH - VEA_OL - VSCRamp - 0.4 0.6 - - V 2.0 - V - - - - - 500 150 80 35 200 - - - - - k dB MHz V/s V Freescale Semiconductor, Inc... Output Voltage Swing - High Level VIN1 > 3.3 V, IOEA = -1.0 mA (Note 7) Output Voltage Swing - Low Level IOEA = -1.0 mA (Note 7) Slope Compensation Ramp (Note 7) OSCILLATOR Oscillator Low Level Output Voltage (Pin CLKSYN), CLKSEL Open Oscillator High Level Output Voltage (Pin CLKSYN), CLKSEL Open Oscillator Input Voltage Threshold (Pin CLKSYN), CLKSEL Grounded Oscillator Frequency Adjusting Reference Voltage (FREQ) Oscillator Frequency Adjusting Resistor Range VOSC_OL VOSC_OH VOSC_IH VFREQ RFREQ - 3.0 1.2 - 100 - - 1.6 1.29 - 0.4 - 2.0 - 200 V V V V k BOOST REGULATOR Boost Regulator Output Voltage IBST = 20 mA, VIN1 = VIN2 = 2.8 V to 6.0 V Boost Regulator Start-Up Voltage Boost Regulator Peak Current Limit (Power FET Peak Current) Boost Regulator Power FET Valley Current Limit (Low Level) Boost Power FET RDS(ON) IBD = 1.0 A, TA = 25C Boost Regulator Recommended Output Capacitor Boost Regulator Recommended Output Capacitor Maximum ESR Notes 7. Design information only. It is not production tested. CBST ESRCBST VIN_BSU IP_BD IL_BD RDS(ON) - - - 150 10 100 400 - - F m VBST 7.5 - 0.75 450 8.0 1.6 1.0 600 8.5 1.8 1.5 800 V A mA m V MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 7 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40C TJ 125C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit LINEAR REGULATOR (LDO) LDO Output Voltage Range VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 10 mA to 1000 mA LDO Feedback Voltage, LFB Pin Connected to LDO Pin VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 10 mA to 1000 mA. Includes Load Regulation Error LDO Voltage Margining Step Size VMLDO REGLNVLDO -1.0 REGLDVLDO -1.0 VLDO_RR - VDO - VCSTH ILDO ILFB ILDRV IDRLIM ICSLK 50 RIN ROUT IQ4_LIM - RDS(ON) - CLDO ESRCLDO TSD TSDHys - - 150 - - 10 TBD 170 15 1.0 - - 190 - F m C C -2.0 - - - - TBD TBD 300 - - A 35 1.6 -5.0 2.0 - - 45 2.0 - 3.6 3.6 TBD 55 2.4 5.0 5.0 - mV mA A mA mA A 40 - V - 1.0 dB - 1.0 % VLDO 0.784 - 0.8 1.0 0.816 - % % VLDO 0.8 - 5.0 V V Freescale Semiconductor, Inc... LDO Line Regulation VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 1000 mA LDO Load Regulation ILDO = 10 mA to 1000 mA LDO Ripple Rejection, Dropout Voltage VDO = 1.0 V, VRIPPLE = +1.0 V p-p Sinusoidal, f = 300 kHz, ILDO = 500 mA LDO Maximum Dropout Voltage (VIN - VLDO) VLDO = 2.5 V, ILDO = 1000 mA LDO Current Sense Comparator Threshold Voltage (VCS - VLDO) LDO Pin Input Current LDO Feedback Input Current (LFB Pin) LDO Drive Output Current (LDRV Pin) LDO Drive Current Limit (LDRV Pin) CS Pin Input Leakage Current VCS = 5.0 V LDO Error Amplifier Input Impedance (LFB Pin) LDO Error Amplifier Output Impedance (LCMP Pin) LDO Pull-Down MOSFET Q4 Current Limit TA = 25C, VBST = 8.0 V (LDO Pin) LDO Pull-Down MOSFET Q4 RDS(ON) ID = 1.0 A, TA = 25C, VBST = 8.0 V LDO Recommended Output Capacitance LDO Recommended Output Capacitor ESR Thermal Shutdown (LDO Pull-Down FET Q4) Thermal Shutdown Hysteresis 33702 8 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40C TJ 125C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit CONTROL AND SUPERVISORY CIRCUITS Enable (EN1, EN2) Input Voltage Threshold Enable (EN1, EN2) Input Voltage Threshold Hysteresis Enable (EN1, EN2) Pull-Down Resistance RESET Low-Level Output Voltage, IOL = 5.0 mA RESET Leakage Current, OFF State, Pulled Up to 5.0 V VTH_EN VIHYS RPU VOL ILKG-RST VOUTITh VOUTITh VLDOITh VLDOITh VTH-RT IS-RT ILKG-RT VSAT-RT Ct VthCLKS RPU-CLKS VthADDR RPU-ADDR 1.2 - 30 - - -10 5.0 -10 5.0 TBD 20 -1.0 - - 1.2 60 1.2 60 1.6 0.1 60 - - -7.5 7.5 -7.5 7.5 1.2 - - 100 - 1.6 120 1.6 120 2.0 - 120 0.4 10 -5.0 10 -5.0 10 TBD 30 1.0 TBD 47 2.0 240 2.0 240 V V k V A % % % % V mA A mV F V k V k Freescale Semiconductor, Inc... RESET Undervoltage Threshold on VOUT (VOUT/VOUT) (Note 8) RESET Overvoltage Threshold on VOUT (VOUT/VOUT) (Note 8) RESET Undervoltage Threshold on VLDO (VLDO/VLDO) (Note 8) RESET Overvoltage Threshold on VLDO (VLDO/VLDO) (Note 8) Reset Timer Voltage Threshold Reset Timer Source Current Reset Timer Leakage Current Reset Timer Saturation Voltage, Reset Timer Current = 300 A Maximum Value of the Reset Timer Capacitor CLKSEL Threshold Voltage CLKSEL Pull-Up Resistance ADDR Threshold Voltage ADDR Pull-Up Resistance SDA, SCL Pins I2C Bus (STANDARD) Input Threshold Voltage Input Voltage Threshold Hysteresis SDA, SCL Input Current, Input Voltage = 0.4 V to 6.0 V SDA Low-Level Output Voltage, 3.0 mA Sink Current SCA, SCL Capacitance Notes 8. This parameter does not include the tolerance of the external resistor divider. VIth VIHYS II VOL CI 1.3 - - - - - 0.2 - - - 1.7 - 10 0.4 10 V V A V pF MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 9 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40C TJ 125C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit BUCK CONVERTER Duty Cycle Range (Normal Operation) Switching Node SW Rise Time (Note 9) ILOAD = 3.0 A Switching Node SW Fall Time (Note 9) ILOAD = 3.0 A Maximum Deadtime (Note 9) tD tPD - tSS tFAULT tRet 200 - - 50 350 10 100 - 800 - - s ms ms tFALL - - D tRISE - 0 - TBD 90 - ns TBD TBD - - ns ns % ns Freescale Semiconductor, Inc... Buck Control Loop Propagation Delay (Note 9) VINV < 0.8 V to VSW > 90% of High Level or VINV > 0.8 V to VSW < 10% of Low Level Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1) Fault Condition Timeout Retry Timer Cycle OSCILLATOR Oscillator Default Frequency (Switching Frequency), FREQ Pin Open Oscillator Frequency Range Oscillator Frequency Accuracy RF = 100 k Oscillator Frequency Accuracy RF = 200 k Oscillator Output Signal Duty Cycle (Square Wave, 180 Out-of-Phase with the Internal Suitable Oscillator) Synchronization Pulse Minimum Duration DOSC tSYNC fOSC 180 - 300 200 50 - 220 % - - ns fOSC fOSC fOSC 360 400 440 kHz 270 200 300 330 400 kHz kHz kHz BOOST REGULATOR Boost Regulator FET Maximum ON Time Boost Regulator Control Loop Propagation Delay (Note 9) Boost Switching Node VBD Rise Time (Note 9) IBST = 20 mA Boost Switching Node VBD Fall Time (Note 9) IBST = 20 mA Notes 9. Design Information only. Not production tested. tB_FALL - 15 40 tON tBST_PD tB_RISE - 15 40 ns - - 24 50 - - s ns ns 33702 10 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40C TJ 125C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit LINEAR REGULATOR (LDO) LDO Output Current Slew Rate Fault Condition Timeout Retry Timer Cycle ISR tFAULT tRet - - - TBD 1.0 100 - - - mA/s ms ms SCA, SCL PIN, I2C BUS (STANDARD) SCL Clock Frequency fSCL tBUF tHD-STA 4.0 tLOW tHIGH tF - tSU-STA tHD-DAT tSU-DAT tSU-STO CB 4.7 0 250 4.0 - - - - - - - 250 - - - - 400 s s ns s pF 4.7 4.0 - - - - - - s s ns 0 4.7 - - 100 - kHz s s Freescale Semiconductor, Inc... Bus Free Time Between a STOP and a START Condition Hold Time (Repeated) START Condition (After this period, the first clock pulse is generated.) Low Period of the SCL Clock High Period of the SCL Clock SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400 pF, 3.0 mA Sink Current Setup Time for a Repeated START Condition Data Hold Time for I2C bus devices (Note 10), (Note 11) Data Setup Time Setup Time for STOP Condition Capacitive Load for Each Bus Line Notes 10. Design Information only. Not production tested. 11. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Timing Diagram tHD-STA tHD-STA tHD-DAT tSU-DAT tSU-STA tSU-STO Figure 2. Definition of Time on the I2C Bus MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 11 Freescale Semiconductor, Inc. Electrical Performance Curves Freescale Semiconductor, Inc... Figure 3. Buck RDS(ON) (Temp) Figure 6. ILIM (Temp) Figure 4. FOSC (RF) Figure 7. Vref (Temp) Figure 5. Buck Efficiency Figure 8. RT Timer (Rt, Ct) 33702 12 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33702 power supply integrated circuit provides the means to efficiently supply the Power QUICC and other families of Motorola microprocessors. It incorporates a highperformance synchronous buck regulator, supplying the microprocessor's core, and a low dropout (LDO) linear regulator providing the microprocessor I/O and bus voltages. This device incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. At the same time, it provides high flexibility of configuration, allowing the maximum optimization of the power supply system. FUNCTIONAL DESCRIPTION Switching Regulator Thermal Shutdown To increase the overall safety of the system designed with the 33702, an internal thermal shutdown function has been incorporated into the switching regulator circuit. The 33702 senses the temperature of the buck regulator main switching FET (high-side FET Q1; see Figure 1), the low-side (synchronous FET Q2), and control circuit. If the temperature of any of the monitored components exceeds the limit of safe operation (thermal shutdown), the switching regulator will be shut down. After the temperature falls below the value given by the thermal shutdown hysteresis window, the switcher will retry to operate again. The VOUT pull-down FET Q3 has an independent thermal shutdown control. When the Q3 temperature exceeds the thermal shutdown limit, the Q3 will be turned off without affecting the switcher operation. Soft Start A switching regulator soft start feature is incorporated in the 33702. The soft start is active each time the IC is enabled, VIN is reapplied, or after a fault retry. Other transient events do not activate the soft start. Freescale Semiconductor, Inc... The switching regulator is a high-frequency (300 kHz default, adjustable in the range from 200 kHz to 400 kHz), synchronous buck converter driving integrated high-side and low-side N-channel power MOSFETs. The switching regulator output voltage is adjustable by means of an external resistor divider to provide the required output voltage within plus/minus two percent accuracy, and it is intended to directly power the core of the microprocessor. The buck controller utilizes a Sensorless PWM Current Mode Control topology to achieve excellent line rejection, stabilize the feedback loop, and provide cycle-bycycle current limiting. A typical bootstrap technique is used to provide voltage necessary to properly enhance the high-side MOSFET gate. When the regulator is supplied only from low-input voltage (e.g., single +3.3 V supply rail), the bootstrap capacitor is charged from the internal boost regulator output VBST through an external diode. This arrangement allows the 33702 to operate from very low input voltage and also comply with the power sequencing requirements of the supplied microcontroller. To avoid destruction of the supplied circuits, a current limit with retry capability was implemented in the switching regulator. When an overcurrent condition occurs and the switch current reaches the peak current limit value, the main (high-side) switch is turned off until the inductor current decays to the valley value, which is one-half of the peak current limit. If an overcurrent condition exists for 10 ms, the buck regulator control circuit shuts the switcher OFF and the switcher retry timer starts to time out. When the timer expires after 100 ms, the switcher engages the start-up sequence and runs for 10 ms, repeatedly checking for the overcurrent condition. During the current limited operation (e.g., in case of short circuit on the switching regulator output), the switching regulator operation is not synchronized to the oscillator frequency. The output voltage VOUT can be adjusted by means of an external resistor divider connected to the feedback control pin INV. The switching regulator output voltage can be adjusted in the range of 0.8 V to 5.0 V, but the VOUT output voltage is always lower than the input voltage to the regulator. Power-up, power-down, and fault management are coordinated with the linear regulator. Boost Regulator A boost regulator provides a high voltage necessary to properly drive the buck regulator power MOSFETs, especially during the low input voltage condition. The LDO regulator external N-channel MOSFET gate is also powered from the boost regulator. In order to properly enhance the high-side MOSFETs when only a +3.3 V supply rail powers the integrated circuit, the boost regulator provides an output voltage of 8.0 V nominal value. The 33702 boost regulator uses a simple hysteretic current control technique, which allows fast power-up and does not require any compensation. When the boost regulator main power switch (low side) is turned on, the current in the inductor starts to ramp up. After the inductor current reaches the upper current limit (nominally set at 1.0 A), the low-side switch is turned off and the current charges the output capacitor through the internal rectifier. When the inductor current falls below the valley current limit value (nominally 600 mA), the low-side switch is turned on again, starting the next switching cycle. After MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 13 Freescale Semiconductor, Inc. the boost regulator output capacitor reaches its regulation limit, the low-side switch is turned off until the output voltage falls below the regulation limit again. thermal shutdown limit, the Q4 will be turned off without affecting the LDO operation. Oscillator A 300 kHz (default) oscillator sets the switching frequency of the buck regulator. The frequency of the oscillator can be adjusted between 200 kHz and 400 kHz by an optional external resistor RF connected from the FREQ pin of the integrated circuit to ground. See Figure 4 for frequency resistor selection. The CLKSYN pin can be configured either as an oscillator output when the CLKSEL pin is left open or it can be used as a synchronization input when the CLKSEL pin is grounded. The oscillator output signal is a square wave logic signal with 50 percent duty cycle, 180 degrees out-of-phase with the internal clock signal. This allows opposite phase synchronization of two 3370x devices. When the CLKSYN pin is used as synchronization input (CLKSEL pin grounded), the external resistor RF chosen from the chart in Figure 4 should be used to synchronize the internal slope compensation ramp to the external clock. Operation is only recommended between 200 kHz and 400 kHz. The supplied synchronization signal does not need to be 50 percent duty cycle. Minimum pulse width is 300 ns. Voltage Margining The 33702 includes a voltage margining feature accessed through the I2C bus. Voltage margining allows for independent adjustment of the Switcher VOUT voltage and the linear output VLDO. Each can be adjusted up and down in 1% steps to a range of 7%. This feature allows for worst case system validation; i.e., determining the design margin. Margining details are described in the section entitled I2C Bus Operation, beginning on page 19 of this datasheet. RESET The RESET pin is an open drain output. The Reset Control circuit supervises both output voltages--the linear regulator output VLDO and the switching regulator output VOUT. When either of these two regulators is out of regulation (high or low), the RESET pin is pulled low. There is a 20 s delay filter preventing erroneous resets. During power-up sequencing, RESET is held low until the Reset Timer times out. Freescale Semiconductor, Inc... Reset Timer Power-Up Delay (RT) The Reset Timer Power-Up Delay (RT) pin is used to set the delay between the time when the LDO and switcher outputs are active and stable and the release of the RESET output. An external resistor and capacitor are used to program the timer. The power-up delay can be obtained by using the following formula: TD = 10 ms + RtCt Where Rt is the Reset Timer programming resistor and Ct is the Reset Timer programming capacitor, both connected in parallel from RT to ground. Note Observe the maximum Ct value and expect reduced accuracy if Rt is less than 10 k. Low Dropout Linear Regulator (LDO) The adjustable low dropout linear regulator (LDO) is capable of supplying a 1.0 A output current. It has a current limit with retry capability. When the voltage measured across the current sense resistor reaches the 45 mV threshold, the control circuit limits the current for 1.0 ms and if the overcurrent condition still exists the linear regulator is turned off. At the same time the overcurrent condition is detected, the Retry Timer starts to time out. When the timer expires after 100 ms, the LDO tries to power up again for 1.0 ms, repeatedly checking for the overcurrent condition. The current limit of the LDO can be set by using the following formula: ILIM = 45 mV/RS Where RS is the LDO current sense resistor, connected between the CS pin and the LDO pin output (see Figure 20). When no current sense resistor is used, it is still possible to detect the overcurrent condition by tying the current sense pin CS to the VBST voltage. In this case, the overcurrent condition is sensed by saturation of the linear regulator driver buffer. The output voltage of the LDO can be adjusted by means of an external resistor divider connected to the feedback control pin LFB. The linear regulator output voltage can be adjusted in the range of 0.8 V to 5.0 V, but the LDO output voltage is always lower than the input voltage to the regulator. Power-up, powerdown, and fault management are coordinated with the switching regulator. Thermal Shutdown The LDO pull-down FET Q4 has an independent thermal shutdown control. When the Q4 temperature exceeds the 33702 14 Watchdog Timer A watchdog function is available via I2C bus communication. It is possible to select either window watchdog or time-out watchdog operation, as illustrated in Figure 9 on page 15. Watchdog time-out starts when the watchdog function is activated via I2C bus sending a Watchdog Programming command byte, thus determining watchdog operation (window or time-out) and period duration (refer to Table 1, page 15). If the watchdog is cleared by receiving a new Watchdog Programming command through the I2C bus, the watchdog timer is reset and the new time-out period begins. If the watchdog time expires, the RESET will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms. After a watchdog time-out, the function is no longer active. MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. Watchdog Closed No Watchdog Clear Allowed 50% of Watchdog Period Watchdog Period Timing Selected via 12C Bus - See Table 1 Window Open for Watchdog Clear EN1 and EN2 Control Pins These two pins permit positive logic control of the Enable function and selection of the Power Sequencing mode concurrently. Table 2 depicts the EN1 and EN2 function and Power Sequencing mode selection. Both EN1 and EN2 pins have internal pull-down resistors and both can withstand a short circuit to the supply voltage, 6.0 V. Table 2. Operating Mode Selection EN1 EN2 0 1 0 1 Operating Mode Regulators Disabled Standard Power Sequencing Inverted Power Sequencing Regulators Enabled, No Power Sequencing Window Watchdog Window Open for Watchdog Clear Watchdog Period Timing Selected via I2C Bus - See Table 1 0 0 1 1 Time-Out Watchdog Freescale Semiconductor, Inc... Figure 9. Watchdog Operation Table 1. Watchdog Programming Command Byte (as a 2nd Command Byte) Address 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Value 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 Action 1st Command WD OFF (Note 12) WD 1280 ms WinOFF WD 320 ms WinOFF WD 80 ms WinOFF WD 20 ms WinOFF WD 1280 ms WinON WD 320 ms WinON WD 80 ms WinON WD 20 ms WinON Power Sequencing Modes The power sequencing of the two outputs of this power supply IC is in compliance with the Motorola Power QUICC and other 32-bit microprocessor requirements. When the input voltage is applied, the switcher and linear regulator outputs follow the supply rail voltage during power-up and power-down in the limits given by the microcontroller power sequencing specification, illustrated in Figures 10 through 12. There are two possible power sequencing modes, Standard and Inverted, as explained in more detail below. The third mode of operation is Power Sequencing Disabled. 3.3 V Input Supply (I/O Voltage) V = 2.0 V Max. Lead V Start-Up 1.8 V Core Voltage Slope 1.0 V/ms (typ.) V = 2.0 V Max. Lead V = 0.4 V Max. Lag Figure 10. Standard Power Up/Down Sequence in +3.3 V Supply System Notes 12. The Watchdog feature will be turned ON automatically after receiving any other valid command byte changing watchdog time. When the Window Watchdog function is selected, the timer cannot be cleared during the Closed Window time, which is 50% of the total watchdog period. When the watchdog is cleared, the timer is reset and starts a new time-out period. If the watchdog is not cleared during the Open Window time, the RESET will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms. V = 2.0 V Max. Lead 5.0 V Input Supply 3.3 V I/O Voltage (VLDO) V = 2.0 V Max. Lead (VOUT) V Start-Up 1.8 V Core Voltage V = 0.4 V Max. Lag V = 0.4 V Max. Lag Figure 11. Standard Power Up/Down Sequence in +5.0 V Supply System MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 15 Freescale Semiconductor, Inc. Standard Power Sequencing V = 2.0 V Max. Lead 5.0 V Input Supply 3.3 V I/O Voltage (VOUT) V Start-Up 1.8 V Core Voltage (VLDO) V = 2.0 V Max. Lead When the power supply IC operates in the Standard Power Sequencing mode, the switcher output provides the core voltage for the microprocessor. This situation and operating conditions are illustrated in Figure 10 and Figure 11. Table 2, page 15, shows the Power Sequencing mode selection. V = 0.4 V Max. Lag V = 0.4 V Max. Lag Inverted Power Sequencing When the power supply IC is operating in the Inverted Power Sequencing mode, the linear regulator (LDO) output provides the core voltage for the microprocessor, as illustrated in Figure 12. Table 2 shows the Power Sequencing mode selection. Figure 12. Inverted Power Up/Down Sequence in +5.0 V Supply System Freescale Semiconductor, Inc... 33702 POWER SEQUENCING Requirements 1. I/O supply voltage not to exceed core voltage by more than 2.0 V. 2. Core supply voltage not to exceed I/O voltage by more than 0.4 V. Standard Power Sequencing Control Comparators monitor voltage differences between the LDO (LDO pin) and the switcher (VOUT pin) outputs as follows: 1. LDO > VOUT + 1.8 V, turn off LDO. The LDO can be forced off. This occurs whenever the LDO output voltage exceeds the switcher output voltage by more than 1.8 V. 2. LDO > VOUT + 1.9 V, shunt LDO to ground. If turning off the LDO is insufficient and the LDO output voltage exceeds the switcher output voltage by more than 1.9 V, a 1.0 shunt FET is turned on that discharges the LDO load capacitor to ground. The shunt FET is used for switcher output shorts to ground and for power down in case of VIN1 VIN2 with the switcher output falling faster than the LDO. 3. LDO < VOUT + 1.7 V, cancel (1) and (2) above, re-enable LDO. Normal operation resumes when the LDO output voltage is less than 1.7 V above the switcher output voltage. 4. LDO < VOUT - 0.2 V, turn off switcher. The switcher can be forced off. This occurs whenever the LDO is less than VOUT - 0.2 V. 5. LDO < VOUT - 0.3 V, turn on Sync (LS) FET and 1.0 VOUT sink FET. The Buck High-Side FET is forced off and the Sync FET is forced on. This occurs when the switcher output voltage exceeds the LDO output by more than 300 mV. 6. LDO > VOUT , reset (4) and (5) above. Normal operation resumes when LDO > VOUT. Methods of Control The 33702 has several methods of monitoring and controlling the regulator output voltages, as described in the paragraphs below. Power sequencing control is also achieved through the intrinsic operation of the regulators. The EN1 and EN2 pins can be used to disable the power sequencing (refer to Table 2, page 15. Intrinsic Operation For both the LDO and switcher, whenever the output voltage is below the regulation point, the LDO external Pass FET will be on or the Buck High-Side FET will be on at a duty cycle controlled by the switcher. Because these devices are FETs, current can flow in either direction, balancing the voltages via the common supply pin. The ability to maintain the FETs on will depend on the available gate voltage, and thus the size of the boost regulator storage capacitor. 33702 16 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. Inverted Power Sequencing Control Comparators monitor voltage differences between the switcher (VOUT pin) and LDO (LDO pin) outputs as follows: 1. VOUT > LDO + 1.8 V, turn off VOUT . The switcher VOUT can be forced off. This occurs whenever the VOUT output voltage exceeds the LDO output voltage by more than 1.8 V. 2. VOUT > LDO + 1.9 V, shunt VOUT to ground. If turning off the switcher VOUT is insufficient and the VOUT output voltage exceeds the LDO output voltage by more than 1.9 V, a 1.0 shunt FET is turned on that discharges the VOUT load capacitor to ground. The shunt FET is used for LDO output shorts to ground and for power-down in case of VIN1 VIN2 with LDO output falling faster than the VOUT . 3. VOUT < LDO + 1.7 V, cancel (1) and (2) above, re-enable VOUT . Normal operation resumes when the VOUT output voltage is less than 1.7 V above the LDO output voltage. 4. VOUT < LDO - 0.2 V, turn off LDO. The LDO can be forced off. This occurs whenever the VOUT is less than VLDO - 0.2 V. 5. VOUT < LDO - 0.3 V, turn on the 1.0 LDO sink FET. This occurs when the LDO output voltage exceeds the VOUT output by more than 300 mV. 6. VOUT > LDO, reset (4) and (5) above. Normal operation resumes when VOUT > LDO. than VOUT, the Buck High-Side FET is also on, and the VOUT load capacitor will be discharged through the Buck High-Side FET to VIN. Thus, provided VIN does not fall too fast, the core voltage (VOUT) will not exceed the I/O voltage (VIN) by more than a maximum of 0.4 V. Shorted Load 1. VOUT shorted to ground. This will cause the I/O voltage to exceed the core voltage by more than 2.0 V. No load protection. 2. VIN shorted to ground. Until the switcher load capacitance is discharged, the core voltage will exceed the I/O voltage by more than 0.4 V. By the intrinsic operation of the switcher, the load capacitor will be discharged rapidly through the Buck High-Side FET to VIN. 3. VOUT shorted to supply. No load protection. 33702 protected by current limit and thermal limit. 2. Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 VIN2 The LDO supplies the microprocessor I/O voltage. The switcher supplies the core (e.g., 1.8 V nominal) (see Figure 11, page 15). Power Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are 2 cases: 1. LDO rises faster than VOUT . The LDO uses control methods (1) and (2) described in the Methods of Control section, page 16. 2. VOUT rises faster than LDO. The switcher uses control methods (4) and (5) described in the Methods of Control section, page 16. Power Down Freescale Semiconductor, Inc... Standard Operating Mode 1. Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V The 3.3 V supplies the microprocessor I/O voltage, the switcher supplies core voltage (e.g., 1.8 V nominal), and the LDO operates independently (see Figure 10, page 15). Power sequencing depends only on the normal switcher intrinsic operation to control the Buck High-Side FET. Power Up When VIN is rising, initially VOUT will be below the regulation point and the Buck High-Side FET will be on. In order not to exceed the 2.0 V differential requirement between the I/O (VIN) and the core (VOUT), the switcher must start up at 2.0 V or less and be able to maintain the 2.0 V or less differential. The maximum slew rate for VIN is 1.0 V/ms. Power Down When VIN is falling, VOUT will be below the regulation point; therefore the Buck High-Side FET will be on. In the case where VOUT is falling faster than VIN, the Buck High-Side FET will attempt to maintain VOUT. In the case where VIN is falling faster This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are 2 cases: 1. VOUT falls faster than LDO. The LDO uses control methods (1) and (2) described in the Methods of Control section, page 16. In the case VIN1 = VIN2, the intrinsic operation will turn on both the Buck High-Side FET and the LDO external Pass FET, and will discharge the LDO load capacitor into the VIN supply. 2. LDO falls faster than VOUT . The switcher uses control methods (4) and (5) described in the Methods of Control section, page 16. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 17 Freescale Semiconductor, Inc. Shorted Load 1. VOUT shorted to ground. The LDO uses method (1) and (2) described in the Methods of Control section, page 16. 2. LDO shorted to ground. The switcher uses control methods (4) and (5) described in the Methods of Control section, page 16. 3. VIN1 shorted to ground. This is equivalent to the LDO output shorted to ground. 4. VIN2 shorted to ground. This is equivalent to the switcher output shorted to ground. 5. VOUT shorted to supply. No load protection. 33702 protected by current limit and thermal limit. the load capacitor will be discharged rapidly through the Pass FET to VIN. 3. LDO shorted to supply. No load protection. 2. Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply VIN1 VIN2 The switcher VOUT supplies the microprocessor I/O voltage. The LDO supplies the core (e.g., 1.8 V nominal) (see Figure 12, page 16). Power Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are 2 cases: 1. VOUT rises faster than LDO. The switcher VOUT uses control methods (4) and (5) described in the Methods of Control section, page 17. 2. LDO rises faster than VOUT . The LDO uses control methods (1) and (2) described in the Methods of Control section, page 17. Power Down This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are 2 cases: 1. LDO falls faster than VOUT . The VOUT uses control methods (4) and (5) described in the Methods of Control section, page 17. In the case VIN1 = VIN2 the intrinsic operation will turn both the Buck High-Side FET and the LDO external Pass FET, and will discharge the VOUT load capacitor into the VIN supply. 2. VOUT falls faster than LDO. The LDO uses control methods (1) and (2) described in the Methods of Control section, page 17. Shorted Load 1. LDO shorted to ground. The VOUT uses methods (4) and (5) described in the Methods of Control section, page 17. 2. VOUT shorted to ground. The LDO uses control methods (1) and (2) described in the Methods of Control section. 3. VIN1 shorted to ground. This is equivalent to the LDO output shorted to ground. 4. VIN2 shorted to ground. This is equivalent to the switcher VOUT output shorted to ground. 5. LDO shorted to supply. No load protection. 6. VOUT shorted to supply. No load protection. 33702 protected by current limit and thermal limit. Freescale Semiconductor, Inc... 6. LDO shorted to supply. No load protection. 33702 protected by current limit and thermal limit. Inverted Operating Mode 1. Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V The 3.3 V supplies the microprocessor I/O voltage, the LDO supplies core voltage (e.g., 1.8 V nominal), and the switcher VOUT operates independently. Power sequencing depends only on the normal LDO intrinsic operation to control the Pass FET. Power Up When VIN is rising, initially LDO will be below the regulation point and the Pass FET will be on. In order not to exceed the 2.0 V differential requirement between the I/O (VIN) and the core (LDO), the LDO must start up at 2.0 V or less and be able to maintain the 2.0 V or less differential. The maximum slew rate for VIN is 1.0 V/ms. Power Down When VIN is falling, LDO will be below the regulation point; therefore the Pass FET will be on. In the case where LDO is falling faster than VIN, the Pass FET will attempt to maintain LDO. In the case where VIN is falling faster than LDO, the Pass FET is also on, and the LDO load capacitor will be discharged through the Pass FET to VIN. Thus, provided VIN does not fall too fast, the core voltage (LDO) will not exceed the I/O voltage (VIN) by more than maximum of 0.4 V. Shorted Load 1. LDO shorted to ground. This will cause the I/O voltage to exceed the core voltage by more than 2.0 V. No load protection. 2. VIN shorted to ground. Until the LDO load capacitance is discharged, the core voltage will exceed the I/O voltage by more than 0.4 V. By the intrinsic operation of the LDO, 33702 18 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. I2C BUS OPERATION Introduction The 33702 device is compatible with the I C interface standard. SDA and SCL pins are the Serial Data and Serial Clock pins of the I2C bus. 2 Table 3. Definition of Selectable Portion of Device Address CLKSEL Pin Low Low Open Open ADDR Pin Low Open Low Open A1 0 0 1 1 A0 0 1 0 1 I2C Command and Data Formats Communication Start Communication starts with a START condition, followed by the slave device unique address. Figure 13 illustrates the data transfer beginning an I2C communication for a 7-bit slave address. Writing Data Into the Slave Device After the address acknowledgment by the slave, DATA can be written into the slave registers. The R/W bit must be set to 0 so DATA will be read. Figure 15 shows the data write sequence. Actions performed by the slave device are grayed. S 7-Bit Address 0 Ack DATA Ack Freescale Semiconductor, Inc... S 7-Bit Address R/W Ack Figure 13. Communication Using 7-Bit Address Slave Address Definition 33702 has the two LSB's address bits defined by the state of the CLKSEL pin and the ADDR pin. Note The state of the CLKSEL pin also defines the configuration of the oscillator synchronization CLKSYN pin. This feature allows up to four 33702 ICs to communicate in the same I2C bus, all of them sharing the same high-order address bits. A different combination of bits A1 and A0 is assigned to each individual part to assure its unique address. Figure 14 illustrates the flexible addressing feature for a 7-bit address. Table 3 provides the definition of the selectable portion of the device address. Bits 6 1 5 1 4321 1 0 1 0 Figure 15. Data Transfer for Write Operations Data Definition For the sake of 33702 acting as a slave device, the master writes a Command Byte and writes one Data Byte. The Command Byte identifies the kind of operation required by the master and has two fields, as illustrated in Figure 16: 1. Address field 2. Value field The address field is selected from the list in Table 4. Bits 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Address Field Value Field A1 A0 Selectable Address Code 001 010 011 Fixed Address Figure 16. Command Byte Table 4. Address Field Definitions Operation Voltage Margining Not Used Watchdog Write W - W Figure 14. Address Bit Definition for 7-Bit Address Refer to Table 5, page 20, which summarizes the value field definitions for the entire set of operation options. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 19 Freescale Semiconductor, Inc. Security in Writing Commands Action 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1st Command Output Normal + 1% + 2% + 3% + 4% + 5% + 6% + 7% - 1% - 2% - 3% - 4% - 5% - 6% - 7% 1st Command WD OFF (Note 13) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 WD 1280 ms WinOFF WD 320 ms WinOFF WD 80 ms WinOFF WD 20 ms WinOFF WD 1280 ms WinON WD 320 ms WinON WD 80 ms WinON WD 20 ms WinON Table 5. Command Byte Definitions Operation Voltage Margining (As a 2nd Command Byte) Address 0 0 0 0 0 0 LDO Output: x=0 Switcher Output x=1 Value 0 x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 All writing operations are critical and must not be inadvertently latched after a false command. To improve the security level, a so-called first command is defined to initiate each write communications. A first command has the Command Byte address field equal to the related operation one, followed by a null value field (all zeros). Table 6 summarizes first command definitions. The master sends the first command before the Command Byte for the intended operation. Table 6. First Command Definitions First Command 001 00000 011 00000 Operation Voltage Margining Watchdog Programming 0 0 0 Freescale Semiconductor, Inc... 0 0 0 0 0 0 0 Watchdog Programming (As a 2nd Command Byte) 0 0 Voltage Margining Operation After starting the communication in Writing mode, the master sends the first command followed by the specific Command Byte to set the required voltage margining for either the LDO or the switcher (see Figure 17). To achieve a simultaneous set for both LDO and switcher, two specific commands must be issued in sequence after the first command, one for each supply. 0 0 1 0 0 0 0 0 Ack 0 0 1 x x x x x First Byte for Voltage Margining Command Byte Figure 17. Voltage Margining Programming (One Supply Only) Note x bits are defined in Table 5. Watchdog Programming Operation For watchdog operation control, the master periodically sends a watchdog first command followed by a command byte selecting, or confirming, the watchdog period according to the options listed in Table 5. Also see Figure 18. The internal watchdog timer will be cleared each time a watchdog command is written into the device, provided it arrives during the window open time. The Command 01100000 sent twice will shut the time OFF, and the watchdog function will be disabled. Any other valid watchdog command turns on the timer again. 0 1 1 0 0 0 0 0 Ack 0 1 1 x x x x x First Byte for Watchdog Programming Command Byte Notes 13. The Watchdog feature will be turned ON automatically after receiving any other valid command byte changing watchdog time. Figure 18. Watchdog Timer Programming Note x bits are defined in Table 5. 33702 20 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. Communication Stop Only the master can terminate the data transfer by issuing a STOP condition. The slave waits for this condition to resume its initial state waiting for the next START condition (see Figure 19). setting for switcher is needed, a fourth byte should be included before the STOP condition (P); for instance, 001 10010 to set switcher in its second setting (switcher output voltage = +2% above its nominal value). Data Transfer Example The master device controlling the I2C bus will always start addressing a 33702 slave IC in writing mode (R/W = 0) in order to be able to write a Command Byte just after the address acknowledge. I2C bus protocol defines this circumstance as a master-transmitter and slave-receiver configuration. Eventually this Command Byte can again define a Write operation (e.g., Voltage Margining, see Figure 19), and the master will keep the data transfer direction. Figure 19 illustrates a communication beginning with the slave address, the first command for voltage margining, and a third byte containing the address field 001 and the value field 00101 corresponding with the LDO fifth setting (LDO output voltage = +5% above its nominal value). If a simultaneous S A6 A5 A4 A3 A2 A1 A0 0 Ack START Slave Address Write 0 0 1 0 0 0 0 0 Ack First Command for Voltage Margining Freescale Semiconductor, Inc... 0 0 1 0 0 1 0 1 Ack P STOP Address Field Value Field = LDO 5th Setting Figure 19. Complete Data Transfer Example MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 21 Freescale Semiconductor, Inc. APPLICATION INFORMATION +3.3 V +3.3V Supply Supply Voltage Voltage VIN1 VIN1 CIN 10uF 10 F VIN VIN VDDI VDDI Internal Supply VBST VBST Vref Power Enable - VDDI VDDI VDDI VDDI VBST VBST 10uF 10 F CBST 8.0V VBST VBST LDRV 1.0 uF QLDO RS 0.068 R 10 H 10uH LBST VBD VBD Freescale Semiconductor, Inc... Boost Control +3.3V +3.3 V or or VLDO VVLDO LDO 5.1k Vref Bandgap Voltage Reference Vref EN1 EN2 Power Sequencing Reset Control RT POR Timer INV LFB 100nF 2 II2C Control Reset RESET to MCU to MCU RESET Reset SysCon RRt t 100k Ct Ct Thermal Limit ADDR Rpd 10k SDA SCL 2 II2C Interface Switcher Oscillator 300kHz Slope Comp. CLKSEL CLKSYN Figure 20. Simplified Block Diagram and Typical Application 33702 22 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com + + + VDDI VDDI VDDI VDDI Linear Regulator Control CS LDO ?k ?k VLDO = 2.5V VLDO = 2.5 V @ 1.0A 1.0 A CLDO 5 x 2.2 uF 5 x 2.2 F Vref II-lim LIM VDDI VDDI LFB VLDO VLDO Pow. Seq. PWR Seq. Power Down UVLO Q4 LCMP 100pF 1.5k 6.8nF Voltage Margining W-dog Timer Watchdog Timer 2 II2 C Control VOUT VOUT Current Limit VBST VBST BOOT VBST VBST VBST VBST VIN2 VIN2 (2) Buck HS & LS Driver Q1 CIN 2 x 10 uF SW Q2 (2) PGND VDDI VDDI SysCon SoftSt Buck Control Logic 2 x 10 F CB +3.3 V +3.3V Supply Supply Voltage Voltage DB 0.1 F 0.1uF L1 4.7 uH 4.7 H VOUT = 1.8V VOUT = 1.8 V CO 50 F 50 uF @ 3.0 A @ 3.0 A ?k PWM Comp. Error Amp. + - + - 0.8V To Reset Control (2) INV ?k ?k Rb VOUT VOUT Pow. PWR Seq. Seq. Q3 VOUT VOUT ? ?pF FREQ RF (Optional) (4) GND Freescale Semiconductor, Inc. PACKAGE DIMENSIONS DWB SUFFIX 32-LEAD SOIC WIDE BODY PLASTIC PACKAGE CASE 1324-02 ISSUE A 10.3 7.6 7.4 C 5 1 32 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. B 9 2.65 2.35 30X 0.65 Freescale Semiconductor, Inc... PIN 1 ID 4 B B 9 11.1 10.9 C L 16 17 5.15 2X 16 TIPS A 32X SEATING PLANE 0.3 ABC A (0.29) 0.25 0.19 A 6 0.13 0.38 0.22 M PLATING M BASE METAL 0.10 A (0.203) R0.08 MIN 0.25 GAUGE PLANE MIN 0 0.29 0.13 CA B 8 8 0 0.9 0.5 SECTION B-B SECTION A-A ROTATED 90 CLOCKWISE MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33702 23 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2003 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors For More Information On This Product, Go to: www.freescale.com MC33702/D |
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